
`include "defines.v"

module inst_rom (
    input  wire              clk,
    input  wire              rst,

    input  wire [`BUS_WIDTH] inst_addr,
    output reg  [31 :     0] inst
);
    
    
    reg [`BUS_WIDTH] rdata;

    RAMHelper rom (
        .clk   (clk),
        .en    (1'b1),
        .rIdx  ({3'b0, ((inst_addr - `PC_START) >> 2'b11)}),
        .rdata (rdata),
        .wIdx  (64'b0),
        .wdata (64'b0),
        .wmask (64'b0),
        .wen   (1'b0)
    );

    assign inst = (rst) ? 32'b0 : (inst_addr[2] ? rdata[63 : 32] : rdata[31 : 0]);


endmodule
